`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:  X-Speed.com.cn
// Engineer: yansf
// 
// Create Date:    01/17/2024 
// Design Name: 
// Module Name:    LEDCtrl 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////


module LEDCtrl(
//-----------CLK
	Clk, 
	nRst, 
//-----------LED_OUT
	LED_BYPASS,
	ERROR_terminal_led_p,
	ERROR_terminal_led_n,
//-----------LED CONTROL INPUT SIGNAL
	BYPASS_STATUS_IN,
//----------error terminal ctrl by reg
	error_out_ctrl,
	nRST_REQ_FrCPU,
	w_total_error
);

input 			Clk;
input			nRst;
input 			BYPASS_STATUS_IN;
input			error_out_ctrl;
input			nRST_REQ_FrCPU;
input			w_total_error;


output 			LED_BYPASS;                 //0:LED is ON      1:LED is OFF
output			ERROR_terminal_led_p;  //pn=10,red     pn=01/11,off    pn=00.green
output			ERROR_terminal_led_n;  

//-----------BYPASS LED CONCTRL
wire 			BYPASS_STATUS_IN;
wire 			LED_BYPASS;
				
assign 			LED_BYPASS = !BYPASS_STATUS_IN;


//-----------ERROR LED CONCTRL
wire			w_total_error;
reg				ERROR_terminal_led_p;
reg				ERROR_terminal_led_n;

	

always @(posedge Clk )
begin
	if( w_total_error == 1'b1 )
			begin
				ERROR_terminal_led_p <= 1'b1;
				ERROR_terminal_led_n <= 1'b0;
			end
	else
		if(!nRST_REQ_FrCPU)
			begin
				ERROR_terminal_led_p <= 1'b1;
				ERROR_terminal_led_n <= 1'b1;
			end
		else
			if( error_out_ctrl == 1'b1 )
				begin
					ERROR_terminal_led_p <= 1'b1;
					ERROR_terminal_led_n <= 1'b0;
				end
			else
				begin
					ERROR_terminal_led_p <= 1'b1;
					ERROR_terminal_led_n <= 1'b1;
				end
end

endmodule